Modern integrated circuit chips are designed in hierarchical fashion, which means that small design pieces are reused to form larger pieces which, in term, are also reused. One of the representations of the chip used in the process of the design is a so-called layout. Layout of the chip includes several two-dimensional representations of each layer of the chip, which is a collection of geometrical shapes that may be stored in some form on a computer. Typically, these geometrical shapes represent some objects on the chip, for example, metal wires, while the space between the layers is filled with non-conducting material (dielectric). To reproduce the complete three dimensional picture of the chip design, additional information about layer thickness and distance between the layers is needed, such information is often called technology information.
Modern chips typically contain millions of active devices, such as transistors, connected by interconnect wires. While a few years ago, the resistance and capacitance, associated with such wires could be neglected, this may no longer be true. In designs at 130 nm and below, interconnect delays determine system performance. Decreasing conductor widths may lead to increased interconnect resistance, while decreasing conductor spacing may cause increased interconnect capacitance. Three-dimensional effects such as fringing and interline coupling are dominant as conductors become taller relative to their width. As a result, parasitic resistance, inductance, and capacitance (RLC) extraction have become a well-established step in the semiconductor chip design and verification process. Since interconnect resistance and capacitance cannot be accounted for during the design stage, accurate calculation of these parameters based on actual chip layout is indispensable for correct chip performance.
Traditionally, extractors of parasitic interconnect RLC values fall into two distinct categories: relatively accurate small-capacity technology computer aided design (TCAD) tools and library-based full-chip pattern matching platforms. TCAD tools typically deal with a small number of three-dimensional (3D) objects and employ numerically-intensive mesh-based (finite element or boundary element) algorithms. Since computational complexity increases super-linearly with the number of elements simulated, no more than several thousands of elements can be handled resulting in accuracy of about few percent for configurations with no more than tens of 3D objects. In the past decade, a number of powerful accelerating techniques, such as a fast multipole method, have been successfully applied to tackle extraction of well-separated conductors and gained popularity for fringe market of printed circuit board (PCB) and packaging designs. Still, these traditional mesh-based approaches have inherent strict capacity limitations for densely-packed IC designs.
In the past decade, the electronic design automation (EDA) industry witnessed the recognition of a different class of TCAD tools based on stochastic methods. Instead of partitioning space or conductor boundaries to large number of elements, capacitance is evaluated by performing multiple random walks of a single “particle” in the dielectric space between the conductors. Because of spatial locality of such walks, even a large number of 3D objects can be handled with a small memory “footprint.” Further, capacitance of large and complex net can be accurately determined using limited number of walks.
Due to inherent capacity and performance limitations, accurate RC extraction methods are impractical or impossible to deal with large full-chip designs. On other hand, importance of post-layout effects demands verification of large industrial size chip. This practical need brought about a class of extraction tools that are based on pattern matching and currently dominate the parasitic extraction market. In such tools, only a fraction of a net is handled in the presence of a few selected adjacent segments. Basically, the complex IC layout is cut and approximately matched to a library of hundreds of pre-solved configurations. In addition shielding and third-body effects are either ignored or treated approximately. Despite huge computational efforts, the pre-built pattern library cannot cover all possible mutual positions of multiple and complex 3D conductors in presence of multilayered dielectrics.
Use of pattern-matching based tools typically does not provide an estimation of the accuracy of obtained results. In addition, such tools depend on a number of “tricks” and other empirical data to ameliorate their poor accuracy. This leads to the use of TCAD tools for result verification, especially for critical nets. Such manual selection and verification process is extremely tedious and is quite far from a “push-button” solution.
With the astonishing pace of semiconductor manufacturing, traditional verification methods, suitable for handling small number of devices, often become un-scalable to handle hundreds of millions of transistors in modern designs. A brute-force approach, based on increased processing speed and proliferation of 64-bit memory platforms, may succeed only for weakly coupled blocks. However, in areas such as dynamic transistor-level simulation or RC extraction, where coupling between objects is strong, the only possible solution to tackle huge designs seemed to be model simplification and reduced accuracy. Recent hierarchical processing has revolutionized these seemingly stagnant market segments providing orders of magnitude performance improvements without sacrifice in accuracy.
Historically, the design of increasingly large IC chips is based on creation of small blocks and combining them together in a hierarchical fashion. Design output formats, from SPICE (Simulation Program with Integrated Circuit Emphasis) netlists to GDSII (Gerber Data Stream Information Interchange) layouts reflect a natural hierarchical structure of design. However, usage of hierarchy in EDA tools is frequently based on repeating results of individual blocks ignoring essential effects of interaction between them. Since results of flattened (slow but accurate) calculations significantly differ from advertised fast hierarchical mode, users have typically abandoned the latter as unreliable.
Failure to appropriately evaluate interconnect effects frequently leads to design respins due to functional and timing violations as well as electromigration degradation.